Design Verification Engineer
Core
Developing verification environments, agents, and test cases for state-of-the-art SoC and embedded IP subsystems using System Verilog and UVM.
Role type
Senior IC ASIC Design Verification Engineer
Builds
High-performance SoC and embedded IP subsystems
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, OVM, C/C++, Perl, scripting, RTL verification methodologies, simulation debugging, coverage analysis, assertion development
Preferred skills
C++/SystemC, Emulators, FPGA prototyping, CPU/DDR/Bus/Network/DSP design knowledge
Technologies
System Verilog, UVM, OVM, C, C++, Perl, SystemC
Responsibilities
Develop verification environments and components (agents, behavioral models), implement coverage and assertions, create random and directed test cases, analyze and debug simulation failures, analyze coverage results
Seniority
Senior, hands-on IC
