ASIC Design Verification Engineer, Technical Leader
Required skills
Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. Prior experience with functional coverage and constrained random DV environments.
Scripting skills
Perl and/or Python scripting
Preferred skills
Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU. Experience with Veloce/HAPS is a plus Formal verification (iev/vc formal) knowledge is a plus
Technologies
System Verilog, UVM methodology, Perl, Python, Veloce/HAPS, formal verification (iev/vc formal)
Responsibilities
Maintaining existing DV environments and enhancing them Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks Write test plan, develop test cases, debug regression failures and drive to module verification closure Ensuring complete verification coverage through implementation and review of code and functional coverage Use AI tools to develop innovative methods and processes to improve quality of design verification.
Seniority
Technical Leader
Domain
ASIC design verification, Silicon One development, AI era hardware platforms
