ASIC Design Verification Engineer, Technical Leader
Core
Lead ASIC design verification for Silicon One hardware platforms, ensuring verification closure through simulation, emulation, and bring-up for Cisco's core Switching, Routing, and Wireless products.
Role type
Senior IC ASIC Design Verification Engineer (Technical Leader)
Builds
ASIC/SoC silicon designs for global networking infrastructure
Domain
Semiconductor hardware design and verification
Required skills
System Verilog, UVM methodology, constrained random verification, functional coverage, test bench development, Perl/Python scripting, complex block/cluster/top-level verification
Preferred skills
Protocol domain expertise (PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU), Veloce/HAPS emulation, formal verification (IEV/VC)
Responsibilities
Maintain and enhance existing DV environments; construct test benches including scoreboards, agents, sequencers, and monitors; write test plans and develop test cases; debug regression failures; drive module verification closure; implement and review code and functional coverage; use AI tools to improve verification processes.
Seniority
Senior, hands-on IC with technical leadership responsibilities
