ASIC Verification Engineer
Core
Architect and build block-level, subsystem, and full-chip verification environments for complex ASICs using SystemVerilog and UVM, ensuring tape-out readiness through rigorous functional and code coverage analysis.
Role type
Senior IC ASIC Verification Engineer
Builds
ASIC chips (networking protocols like Ethernet)
Domain
Semiconductor / Hardware Design / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production hardware verification environments and test suites
Required skills
SystemVerilog, UVM (Unified Verification Methodology), constrained-random verification, Perl/Tcl/Python/Shell scripting, gate-level simulation analysis, debugging complex design issues
Preferred skills
Ethernet protocol verification, OVM/VMM methodologies
Technologies
SystemVerilog, UVM, VCS, NC, Perl, Python, Shell, Tcl
Responsibilities
Develop and enhance ASIC verification environments; Define, design, and execute verification suites and test cases; Independently verify large ASIC blocks and drive tape-out readiness; Collaborate with logic designers to debug and resolve design issues; Develop automation scripts for verification infrastructure
Seniority
Senior, hands-on IC
