DFT Architect
Core
Define and govern next-generation DFT architecture for advanced FPGA, SoC, and multi-die silicon platforms, ensuring world-class testability and manufacturability.
Role type
Senior IC DFT Architect
Builds
Scalable DFT solutions for high-performance compute, AI acceleration, and heterogeneous integration
Domain
Semiconductor / FPGA / SoC / Advanced Packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT strategy definition, scan architecture, ATPG, MBIST/LBIST, hierarchical DFT, IJTAG/IEEE standards, silicon debug, production test optimization, cross-functional leadership, technical mentorship, EDA tool strategy
Preferred skills
Advanced fault models and diagnosis, silicon analytics, 2.5D/3D IC and chiplet architectures, high-speed IO/SerDes DFT, power-aware DFT, low-power ATPG, AI-integrated DFT methodologies
Technologies
Perl, Python, TCL, IEEE 1687, IEEE 1149.x, EDA synthesis and verification tools
Responsibilities
Define long-term DFT architecture for complex silicon programs; Lead development of scalable DFT methodologies across RTL to gate-level; Architect state-of-the-art scan, compression, and in-system test solutions; Drive DFT planning for multi-die and advanced packaging systems; Collaborate with architecture, RTL, PD, and validation teams; Establish and enforce DFT guidelines and signoff criteria; Lead root-cause analysis for test failures and yield issues; Optimize production test strategies for coverage and efficiency; Mentor DFT engineers and drive cross-functional alignment; Partner with EDA vendors to deploy advanced tool capabilities
Seniority
Senior, hands-on IC with strategic oversight
