DFT Architect
Core
Define, drive, and govern next-generation DFT architecture for advanced FPGA, SoC, and multi-die silicon platforms to ensure world-class testability, manufacturability, and silicon quality.
Role type
Senior DFT Architect (Silicon/SoC/FPGA)
Builds
Scalable DFT solutions for complex, large-scale silicon programs including FPGA, SoC, processor, DSP, SERDES, IO, and multi-die/chiplet-based products.
Domain
Semiconductor / FPGA / SoC / Advanced Packaging
Required skills
DFT strategy ownership, scan architecture, ATPG, compression, MBIST, LBIST, boundary scan, hierarchical DFT, RTL-to-GDS integration, silicon debug, manufacturing test optimization, EDA tool strategy, technical mentorship, scripting (Perl, Python, TCL)
Preferred skills
Advanced fault models and diagnosis, silicon analytics, 2.5D/3D ICs and chiplet architectures, high-speed IO/SerDes DFT, power-aware DFT, low-power ATPG, AI-integrated DFT methodologies
Technologies
Scan, Compression, MBIST, LBIST, IJTAG, JTAG, Perl, Python, TCL, EDA tools
Responsibilities
Define long-term DFT architecture for multi-die and chiplet products; Lead development of scalable DFT methodologies across RTL and gate-level; Architect state-of-the-art scan, compression, and in-system test solutions; Drive DFT planning for 2.5D/3D ICs and heterogeneous systems; Collaborate with architecture, RTL, PD, and validation teams; Establish and enforce DFT guidelines and signoff criteria; Lead root-cause analysis for pre- and post-silicon test failures; Optimize production test strategies for yield and efficiency; Mentor DFT engineers and drive cross-functional alignment; Partner with EDA vendors to deploy advanced tool capabilities.
Seniority
Senior, hands-on IC with strategic leadership
