Principal DFT Engineer
Core
Architecting, implementing, and verifying advanced DFT solutions for complex digital ASICs and SoCs to ensure robust testability and manufacturing yield.
Role type
Principal Digital DFT Engineer
Builds
Digital ASICs and SoCs with embedded DFT structures
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (DFT flows, test structures, test strategies)
Required skills
DFT architecture definition, scan insertion, ATPG, boundary scan, MBIST, logic BIST, JTAG, test compression, EDA tool usage, fault simulation, RTL design knowledge, SoC architecture constraints, DFT automation scripting, technical documentation, mentorship
Preferred skills
Advanced node DFT (≤ 7nm), 2.5D/3D packaging DFT, high-speed IP DFT, production ATE pattern development, safety/security-oriented DFT, memory BIST
Technologies
Synopsys DFT Compiler, Tessent, Cadence Modus, TCL, Python, Perl
Responsibilities
Own DFT architecture and implementation for digital chips; execute EDA tools for scan synthesis and test generation; create and validate test plans for high fault coverage; integrate DFT with RTL and physical design teams; optimize test modes and debug silicon failures; develop low-overhead test structures; debug DFT issues in simulation, emulation, and lab; deliver DFT architectures and guidelines; collaborate with ATE engineers; mentor engineers in DFT methodology.
Seniority
Principal, hands-on IC with mentorship
