Lead DFT Engineer
Core
Lead DFT implementation and signoff for complex SoC/ASIC designs from RTL to silicon validation.
Role type
Lead DFT Engineer
Builds
Testable silicon with high fault coverage and robust quality
Domain
Semiconductor / ASIC Design
Required skills
ATPG, LBIST, MBIST, Scan Insertion, Scan Compression, JTAG/iJTAG, Low-power DFT, Testability Analysis, Silicon Debug
Preferred skills
Boundary Scan standards (1149.1, 1500, 1687), Cross-functional collaboration
Technologies
RTL, SoC, ASIC
Responsibilities
Lead end-to-end DFT implementation for SoC subsystems, Drive DFT RTL integration and verification, Implement full-scan DFT methodologies, Develop and optimize scan insertion and compression, Execute ATPG flows to achieve required fault coverage, Define and implement MBIST architectures including repair flows, Support silicon debug and failure analysis
