Lead DFT Engineer
Core
Lead DFT implementation and signoff for complex SoC/ASIC designs from RTL to silicon validation.
Role type
Lead DFT Engineer
Builds
SoC/ASIC designs with high test coverage and robust silicon quality
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ATPG, LBIST, Scan Insertion, Scan Compression, iJTAG (IEEE 1687), MBIST architectures, Boundary Scan / JTAG, Low-power DFT, Testability analysis, Silicon debug
Preferred skills
Repair flows, Test coverage optimization
Technologies
IEEE 1149.1, IEEE 1500, IEEE 1687
Responsibilities
Lead end-to-end DFT implementation for SoC subsystems, Drive DFT RTL integration and verification, Implement full-scan DFT methodologies, Develop and optimize scan insertion and compression techniques, Execute ATPG flows to achieve required fault coverage, Define and implement MBIST architectures including repair flows, Support silicon debug and failure analysis
Seniority
Senior, hands-on IC
