Staff Silicon Power & Performance Engineer (System Level Test & Characterization)
Core
Plan and execute silicon power, performance, and thermal characterization activities across multiple projects to ensure flawless silicon performance.
Role type
Staff System Level Test and Characterization Engineer
Builds
Scalable automation frameworks, regression infrastructure, data collection flows, dashboards, and reporting tools.
Domain
Semiconductor / SoC Power & Performance
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Post-silicon characterization, SoC IP characterization (CPU, interconnect, DDR, PCIe, UCIe), lab equipment operation (oscilloscopes, DAQ, thermal chambers, power analyzers), power and performance optimization, benchmarking and profiling tools (SPEC2017, LMBench, Stress-ng, Fio, iPerf), VRMs/PMICs/voltage rails understanding, large dataset analysis, firmware/bootloader/UEFI/BIOS/ACPI/device tree flows
Preferred skills
VMIN analysis, pre-silicon modeling/simulation/emulation/FPGA, pre- and post-silicon power/performance correlation, scripting (Python, Shell, Perl), C/C++ programming, silicon bring-up, board enablement, power management features (DVFS, AVS, thermal throttling), Arm/SoC architecture understanding
Technologies
SPEC2017, LMBench, Stress-ng, Fio, iPerf, Python, Shell, Perl, C, C++, UEFI, BIOS, ACPI, device tree
Responsibilities
Plan and execute Silicon PVTF characterization activities across multiple projects and platforms; Develop scalable automation frameworks, regression infrastructure, data collection flows, dashboards, and reporting tools; Analyze leakage/static, active-idle, dynamic, and Silicon boot power to identify bottlenecks and optimization opportunities; Characterize voltage droop and loadline impedance; Enable and port industry-standard, customer, and stress workloads required for silicon characterization; Collaborate with SoC architecture, firmware, validation, and systems teams to debug and resolve silicon issues
Seniority
Staff, hands-on IC
