ASIC Verification Engineering
934 open positions
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Staff Design Verification Engineer ArmAustin, Texas $250k–$250k3mo Develop SystemVerilog/UVM testbenches for unit-level verification of Memory Controller functional units, ensuring PPA goals are met.
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Sr. Staff Verification Engineer SemtechIND - Hyderabad 3mo Define, develop, and optimize verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits.
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Senior Chip Design Verification Engineer, Port IP Group NVIDIAIsrael, Tel Aviv 3mo Chip Design Verification Engineer developing front-end design for Switch silicon, GPU, and HCA with focus on high-speed communication devices.
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Verification Engineer - GPU / Semiconductor↗ European Tech RecruitCork, County Cork, Ireland 3mo Develop performance verification tests, debug GPGPU architecture bottlenecks, and deploy verification methodologies for GPU products.
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<Data Center>ASIC Testing Integration Engineering MediaTekHsinChu 3mo Define DFT architecture specifications and manage post-silicon test flow optimization for MTK ASIC product portfolios.
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Digital Design Verification Engineer | Precision ADC Texas InstrumentsTucson, AZ, United States 4mo Develop SystemVerilog/UVM testbenches to verify digital logic, calibration algorithms, and mixed-signal interfaces of high-resolution delta-sigma ADC signal chains.
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Senior Engineer in Product Engineering, NAND Validation MicronMSB, Singapore 4mo Design and execute functional and design validation flows for advanced NAND devices using silicon and simulation platforms, applying AI/ML techniques to improve test efficiency and debug productivity.
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Staff DFT Engineer AnalogdevicesIndia, Bangalore, RMZ 4mo Own and drive the complete DFT strategy for complex SoCs from architecture through production silicon, ensuring test quality, coverage, and silicon readiness.
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Senior/Staff Design for Test Engineer OlixAustin, TX 4mo Architect, own, and implement comprehensive Design-for-Test (DFT) strategies for complex high-throughput digital pipelines in advanced CMOS nodes to ensure high test coverage and efficient test execution for next-generation AI accelerators.
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Emulation Engineer
MatXMountain View (HQ) or Remote
$160k–$160k4mo
Building infrastructure, flows, and debug methodology for advanced connectivity SoCs to support high-performance GenAI silicon.
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Staff Design Verification Engineer – Coherent Interconnect SifiveBoston, Massachusetts, United States 4mo Drive verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs, focusing on CXL protocol behavior, bridge paths, and subsystem integration.
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DFT Engineer GlobalFoundriesRichardson $106k–$106k4mo Designing and deploying advanced Design-for-Test (DFT) solutions for semiconductor chip development, focusing on robust architectures and optimized test methodologies.
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Formal Verification Engineer
MatXMountain View (HQ) or Remote
$160k–$160k4mo
Apply model checking and formal property verification to RTL blocks, memory subsystems, and interconnects; develop machine-checked proofs for compiler transformations; embed hardware description languages and simulator models into interactive theorem provers…
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Mixed-Signal Verification Engineer – Analog IP ON SemiconductorAllen, TX, United States 4mo Develop and execute mixed-signal verification solutions for analog IP blocks integrated into digital-on-top SoC environments on the Treo platform.
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IP Design Verification Engineer Samsung ElectronicsSSIR, Goldstone, Bangalore, India 4mo Design and verify high-speed serial IP blocks (SERDES, PCIe, Ethernet) and security IP (AES, SHA, secure-boot) using UVM-based environments.
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Principal SOC Verification Engineer NxpNoida 4mo Lead end-to-end verification for ARM-based automotive MCUs, ensuring tape-out readiness through full-chip integration and sign-off ownership.
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ASIC Verification Engineer AxiadoTaipei, tw 4mo RTL SoC/Subsystem verification of ARM based SoCs for Smart Edge SoCs used in network/systems control, management security systems, and IIoT.
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Senior Quantum Analog Mixed-Signal Verification Engineer MicrosoftUnited States, Washington, Redmond 4mo Creating system-wide Analog Mixed-Signal (AMS) models, simulation environments, and test plans for System-on-a-Chip (SoC) and Intellectual Property (IP) blocks, integrating analog and digital blocks for system-level algorithm modeling.
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