Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)
Core
Develop, maintain, and enhance block-level and sub-system testbenches for CPU IP to ensure highest quality in the ASIC design cycle.
Role type
CPU Verification Engineer (RAS)
Builds
CPU IP blocks and subsystems for RISC-V architecture
Domain
Semiconductor / Chip Design / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, constrained-random stimulus generation, coverage-driven verification, computer architecture (pipelines, memory hierarchies, caches), scripting (Python, Perl, Bash)
Preferred skills
RAS architecture, ECC testing, parity generation/checking, data poisoning, hardware fault injection, RISC-V ISA
Technologies
System Verilog, UVM, Python, Perl, Bash
Responsibilities
Develop and maintain block-level and sub-system testbenches; Extract verification requirements from architecture specifications; Write directed and constrained-random tests; Debug simulation failures and collaborate with RTL designers; Maintain and optimize automated regression setups
Seniority
Entry to Senior IC
