Principal Verification Engineer
Core
Developing comprehensive verification strategies and plans for power management integrated circuits to ensure functional and code coverage.
Role type
Principal Verification Engineer (SoC/Block-level)
Builds
Scalable and reusable verification environments for power management ICs
Domain
Semiconductor / Power Management ICs
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, formal verification, Assertion-Based Verification (SVA/PSL), Python/Tcl/C-shell scripting, debugging complex verification issues, technical leadership, analog/mixed-signal IC architecture knowledge
Preferred skills
Power-aware verification (UPF/UCF), AI/ML techniques in verification, HW/SW co-verification, requirements/project management tools
Technologies
SystemVerilog, UVM, EDA tools, Python, Tcl, C-shell, JAMA, JIRA
Responsibilities
Develop SoC, subsystem, and block-level verification plans; Build and maintain scalable verification environments; Drive verification quality to achieve coverage metrics; Analyze and root-cause verification failures; Lead verification activities from planning to silicon validation readiness
Seniority
Principal, hands-on IC with technical leadership
