Verification Lead (Lead DV)
Core
End-to-end verification lead for a first-of-its-kind chiplet, defining methodology, coverage strategy, and regression infrastructure before RTL availability.
Role type
Senior IC ASIC/SoC verification lead
Builds
Chiplet verification infrastructure, UVM architecture, and signoff criteria for optical interconnects and photonic engines
Domain
Semiconductor hardware verification (ASIC/SoC) for AI supercomputing photonics
Deliverable
production ML models
Required skills
ASIC/SoC verification, UVM/SystemVerilog, coverage-driven verification, constrained-random methodology, hardware-assisted verification (emulation/FPGA), mixed-signal verification, regression/CI automation, team leadership
Preferred skills
High-speed SerDes/PAM4/FEC verification, UCIe/PCIe/CXL link-layer VIP, low-power/UPF methodology, formal verification, performance verification
Technologies
UVM, SystemVerilog, Palladium, Veloce, HAPS, Protium, Verilog-AMS, UPF
Responsibilities
Define full DV strategy and coverage model; stand up regression/CI infrastructure; verify engines against golden models with error injection; own emulation/FPGA prototyping; handle UCIe VIP and compliance; lead and grow the DV team
Seniority
Senior, hands-on IC with team leadership
