ASIC Design Verification Engineer
Core
Constrained Random Design Verification engineer developing high throughput Ethernet solutions for AI/ML workflows in silicon products.
Role type
Senior ASIC Design Verification Engineer
Builds
High throughput Ethernet devices for Cloud and AI/ML acceleration
Domain
Semiconductor / Ethernet / AI/ML infrastructure
Deliverable
production ML models
Required skills
Constrained random verification, coverage closure, System Verilog, UVM, OOP
Preferred skills
Python scripting, Perl scripting
Technologies
System Verilog, UVM, VCS, Incisive
Responsibilities
Develop leading edge products with worldwide design and architecture teams, drive completion via coverage closure, verify new designs evolving rapidly
Seniority
Senior, hands-on IC
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