Principal Design Verification Engineer
Core
Design verification for wireless communication ASICs, focusing on digital IP blocks, circuit calibration, DSP, and CPU subsystems.
Role type
Principal Design Verification Engineer
Builds
Wireless communication ASICs
Domain
Semiconductor / Hardware Engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained random stimulus, assertions, UPF, Python/Perl/Tcl scripting, EDA tools, digital simulators, waveform viewers, build/run automation, gate level simulations
Preferred skills
C/C++, formal verification, digital logic design, micro-processor architecture, DFT architecture, CPU microarchitecture, communication chip experience
Technologies
SystemVerilog, UVM, Python, Perl, Tcl, UPF
Responsibilities
Maintain and develop SystemVerilog/UVM test benches for digital IP blocks; Create constrained random stimulus and write checkers/assertions; Analyze simulation results and debug issues; Verify power intent using UPF; Develop scripts to improve task efficiency; Collaborate with digital IP design teams to develop comprehensive test strategies.
Seniority
Senior, hands-on IC
