Lead DFT Engineer - MBIST
Core
Architecting, implementing, and validating advanced Design-for-Test (DFT) solutions for complex System-on-Chips (SoCs), focusing on memory testing and scan insertion.
Role type
Senior IC DFT Engineer (MBIST/SCAN/ATPG)
Builds
Testable SoC designs with embedded memory BIST and scan chains
Domain
Semiconductor manufacturing / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
MBIST architecture, Scan Insertion, ATPG, RTL DFT verification, Gate-Level Simulation (GLS), Tcl/Python/Shell scripting, ATE debugging, Redundancy Analysis (RA), SDC timing closure
Preferred skills
RTL development, Functional verification of logic circuits
Technologies
Tessent, SystemVerilog, UVM, Tcl, Python, Shell, SDF
Responsibilities
Define and implement DFT architecture including Scan, MBIST, and Test Access Mechanisms; Lead Scan Insertion and ATPG Pattern Generation; Develop and integrate MBIST solutions for embedded memories (SRAM/MRAM/ROM); Perform RTL-level DFT verification and debug; Execute and debug Gate-Level Simulations (GLS) with SDF back-annotation; Collaborate with Physical Design teams for scan chain stitching, reordering, and timing closure; Support silicon bring-up and ATE debugging.
Seniority
Senior, hands-on IC
