ASIC Verification Engineering

928 open positions

Design Verification Engineer - Internal IP EtchedSan Jose 1y Develop and maintain UVM/SystemVerilog testbenches to validate custom IPs (systolic arrays, DMA engines, NoCs) for high-performance inference chips.
Performance IP Design Verification Lead MediaTekAustin, TX 1y Managing and guiding a team of engineers to ensure the functional verification of complex digital IP blocks for Flagship Smartphone/Compute SOCs.
Senior Chip Design Engineer NVIDIAIsrael, Tel Aviv 1y FullChip verification technical lead designing and implementing next-generation high-speed Switch Silicon chips for NVIDIA's Networking business unit.
Senior Chip Design Verification Engineer NVIDIAIsrael, Tel Aviv 1y Design and verify Phy Layer IP blocks for high-speed networking silicon chips, building reference models and simulating chip entities to meet performance requirements.
<Data center>DFT senior engineer MediaTekHsinChu 1y Define and implement DFT architectures for data center ASIC products to ensure robust test solutions, yield improvement, and quality for mass production.
Staff/Senior Staff Engineer - AMS Verification SilabsHyderabad 1y Design verification of next generation IP/SoCs with emphasis on verifying and signing off performance, power, and functionality using RNM models.
Lead Hardware Engineer - DFT IP R&D CadenceNOIDA, IN 1y Developing cutting-edge Design-for-Testability (DFT) tools and IP for the MODUS software solution to achieve high coverage and reduced test time.
Principal Design Engineer CadenceBANGALORE 1y Design Verification for interconnect IP, crafting verification plans, and ensuring coverage closure for highly complex and configurable designs.
Principal Engineer Renesas-ElectronicsNoida, in 1y Lead full-chip emulation and FPGA prototype development for complex automotive SoC designs to ensure zero-bug silicon tape-out.
Senior DFT Engineer Texas InstrumentsBengaluru, Karnataka, India 1y Design for Testability (DFT) architecture and implementation for automotive-grade System-on-Chips (SoCs) and microcontrollers, ensuring safety and security standards for logic and memory tests.
Sr Principal Design Engineer CadenceNOIDA 1y Manage a Memory Controller Design Verification (DV) group focusing on MDV verification, including constrained random functional verification, formal property verification, and project execution.
Lead Design Engineer CadenceBANGALORE 1y Lead Design Engineer responsible for IP integration, verification, and release of Cadence's IP solutions for customers.
DFT Engineer MediaTekBangalore 1y Developing and optimizing Design for Test (DFT) strategies for System-on-Chip (SoC) and Modem in smartphones, focusing on pre-silicon verification and post-silicon debug.
DFT 高级工程师 MediaTekBeijing 1y Designing and implementing SOC/IP DFT architectures, ATPG, and pattern simulation to ensure silicon testability.
Senior IC Verification Engineer（MBJ） MediaTekBeijing 1y Developing and maintaining SoC/IP verification flows and participating in verification across different chip levels.
Principal Design Engineer CadenceBANGALORE, IN 2y Lead design verification for complex electronic designs, specifically focusing on memory IP verification.
<Automotive>Security Hardware IP Digital IC Engineer MediaTekChuPei 2y Design and verify security hardware intellectual property (IP) for automotive applications.
SoC Debug IC Designer MediaTekTaipei 2y Design, implement, and verify debug modules (trace, monitor, access ports) for SoC platforms to support issue localization and performance optimization.
Principal Design Engineer CadenceBANGALORE 2y Design Verification Engineer for Serial and Interface Design IPs (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) within the IP development team.
Lead Design Engineer CadenceBANGALORE 2y Lead Design Engineer responsible for functional verification of complex electronic designs and memory IP.
Principal DFT Design Engineer CadenceBANGALORE 2y Designing and implementing Design for Test (DFT) methodologies to enhance chip quality, reliability, and in-system test/debug capabilities.
SoC Design Verification Engineer MatXMountain View (HQ) or Remote $160k–$160k2y Deliver performant and functionally accurate silicon for high-performance GenAI products across compute, memory management, and high-speed connectivity.
Functional Modeling Engineer MediaTekBangalore 2y Develop and verify SystemC Functional / TLM models of components in automotive System-on-Chip (SoC) and provide stimulus and checkers for top-level virtual platform integration.
Lead Product Engineer - Design Verification (MM/VIP) CadenceAHMEDABAD, IN 2y Lead Product Engineer driving adoption of Cadence's Memory Verification IP (VIP) portfolio for protocols like DDR5, GDDR6, and DFI, supporting pre-sales and customer design flows.
Design Verification Engineer MediaTekBangalore 2y Architecting and developing testbenches and test-bench components for ISA, clock, reset, and power features of processors.
<Automotive>SoC Chip Design Engineer for DFT/DFM MediaTekHsinChu 3y Designing and implementing DFT/DFM methodologies for automotive ADAS SoC chips to ensure testability and manufacturability.
Design Verification Engineer MediaTekHsinChu 7y Developing and implementing verification plans for smartphone, TV, and ASIC product lines within the Mediatek chip development flow.
RTL Verification Engineer (On-site. Bengaluru, India) IxanaBengaluru, India Verify cutting-edge SoCs and IPs for AI-powered wearables using Wi-R, a patented non-radiative near-field communication technology.

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