Senior Engineer, Design Verification (MCU)
Core
End-to-end verification execution for SoCs owning complex digital IP's and subsystems, from specification to sign-off.
Role type
Senior IC design verification engineer (MCU/SoC)
Builds
Scalable, reusable UVM-based verification environments and robust verification plans/checkers for IP and subsystems.
Domain
Semiconductor / Digital IC Design / Verification
Required skills
SystemVerilog, UVM, assertions (SVA), constrained-random verification, directed test methodologies, coverage closure, EDA toolkits, MCU architectures (ARM Cortex-M, RISC-V), embedded peripherals (AHB/APB/AXI, GPIO, UART, SPI, I2C, CAN), low-power verification, post-silicon debug.
Preferred skills
AI/ML-assisted verification techniques, Python/Perl/TCL scripting, formal verification, firmware-driven verification, ISO 26262 functional safety concepts, embedded C/RTOS debugging.
Technologies
UVM, SystemVerilog, SVA, EDA tools, Python, Perl, TCL, ARM Cortex-M, RISC-V, AHB, APB, AXI, GLS, Emulation.
Responsibilities
Define and drive IP-level verification strategies including test plans and coverage models; Develop scalable UVM-based verification environments; Lead functional, code, assertion, and cross-coverage closure; Apply AI/ML-assisted verification techniques to accelerate coverage convergence; Collaborate with RTL, Architecture, and Emulation teams; Mentor junior engineers and promote best-in-class verification practices.
Seniority
Senior, hands-on IC
