Pre-Silicon Validation Engineer
Core
Develop, deploy, and maintain ASIC/FPGA emulation environments for complex SoC designs to enable early hardware/software co-validation.
Role type
Junior/Senior Emulation Engineer (Pre-Silicon Validation)
Builds
ASIC/FPGA emulation environments and verification infrastructure for SoC designs
Domain
Semiconductor / Hardware Verification
Required skills
SystemVerilog, C/C++, Python, Linux shell scripting, RTL debugging, waveform analysis, SoC architecture knowledge, bus protocols
Preferred skills
Cadence Palladium/Protium, Siemens Veloce, Synopsys ZeBu, Xilinx/Intel FPGA flows, PCIe/CXL/DDR/Ethernet interfaces, cloud-based compute environments, AI/ML engineering tools
Technologies
Cadence Palladium, Siemens Veloce, SystemVerilog, C/C++, Python, Linux, Xilinx, Intel, PCIe, CXL, DDR, Ethernet
Responsibilities
Develop and maintain emulation environments for complex SoC designs; Port RTL designs onto emulation platforms; Develop testbenches and verification infrastructure; Analyze and debug functional and system-level issues; Create automation scripts for regression and debug; Collaborate with design teams to optimize emulation performance; Apply AI-assisted tools to accelerate verification and debug.
Seniority
Junior/Senior, hands-on IC
