ASIC Verification Engineer
Core
Lead block-level and top-level ASIC and IP verification efforts for 5G network products, architecting RTL testbenches and driving verification strategies.
Role type
Senior IC ASIC verification engineer (5G IP)
Builds
Functional RTL blocks for integration into 5G ASICs
Domain
Semiconductor / 5G Networks
Required skills
SystemVerilog, UVM, RTL debugging, TLM, SerDes, PCIe, ARM subsystems, DSPs, Ethernet, scripting (TCL/Python/Perl), technical leadership
Preferred skills
Hardware emulation, behavioral modeling, SW-driven verification, mentoring
Technologies
SystemVerilog, UVM, TLM, SerDes, PCIe, ARM, DSPs, Ethernet
Responsibilities
Architect and develop comprehensive RTL testbenches from scratch, Conduct hands-on verification utilizing SystemVerilog and UVM methodologies, Participate in hardware emulation and hardware acceleration verification, Drive SW-driven verification initiatives, Mentor team members and contribute to technical leadership, Participate in defining verification strategies and best practices
Seniority
Senior, hands-on IC
