Senior ASIC Design Verification Engineer
Core
Plan, build, and execute verification of new and existing features for AMD's graphics processor IP to ensure a bug-free final design.
Role type
Senior IC ASIC design verification engineer
Builds
Graphics processor IP
Domain
Semiconductors / ASIC Design
Required skills
UVM, SystemVerilog, Verilog, C++, C, Linux, debugging firmware and RTL, test plan creation, coverage analysis
Preferred skills
Graphics pipeline knowledge, UVM framework development, distributed compute automation, HLS tools, SystemC, TLM, scripting (Perl, Ruby, shell), leadership/mentorship
Technologies
UVM, SystemVerilog, Verilog, C++, C, Linux, Windows, HLS, SystemC, TLM, Perl, Ruby, Makefile
Responsibilities
Collaborate with architects and hardware engineers to understand features; Build test plans; Estimate test development time; Build directed and random verification tests; Debug test failures and resolve design defects; Review functional and code coverage metrics
Seniority
Senior, hands-on IC
