Design Verification Engineer - Haifa
Core
Develop and execute verification plans for complex connectivity IPs within Qualcomm SOCs, focusing on low power and high performance.
Role type
Junior IC design verification engineer (VLSI)
Builds
High-speed interface connectivity IPs for Snapdragon SoCs
Domain
Semiconductor / VLSI / Wired Connectivity
Required skills
SystemVerilog, UVM, directed testing, constrained-random testing, assertion development, functional coverage modeling, RTL debugging, regression analysis
Preferred skills
Verilog, verification experience, strong programming background
Responsibilities
Develop and execute verification plans for complex connectivity IPs; Build, enhance, and maintain SystemVerilog/UVM verification environments; Create directed, constrained-random, stress, performance, power, and system-level test scenarios; Develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics; Debug RTL, testbench and silicon bring-up issues using logs, waveforms, traces, and hardware debug data; Drive coverage closure, regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.
