SR ENGINEER, HIG HBM SOC VERIFICATION
Core
Develop test plans, build verification environments, and debug pre/post-silicon issues for complex HBM (High Bandwidth Memory) System-on-Chips (SOCs) and architectures.
Role type
Senior IC verification engineer (HBM/SOC)
Builds
Verification environments and test plans for HBM products
Domain
Semiconductor / Memory / HBM
Required skills
System Verilog, UVM, Python, Gate-level simulation (GLS), UCIE, memory controller, NOCs, MBIST, ATPG scan controllers, DRAM operation, JEDEC specifications
Preferred skills
None stated
Technologies
System Verilog, UVM, Python, UCIE, GLS
Responsibilities
Develop test plans at SOC Level and analyze Coverage; Build verification environments to verify complex SOCs; Develop Random/Directed test in RTL and GLS environments; Debug and identify root causes and solutions for pre-silicon and post-silicon issues; Work with IP suppliers to ensure proper verification and validation collaterals are provided; Engage with customers to understand verification and validation requirements.
Seniority
Senior, hands-on IC
