IP Verification Engineer
Core
Senior Design Verification Engineer building and validating RTL blocks for Ericsson's 5G ASIC IP, ensuring silicon reliability for global 5G infrastructure.
Role type
Senior IC Design Verification Engineer (ASIC IP)
Builds
Functional RTL blocks for 5G network infrastructure
Domain
Telecommunications / Semiconductor / 5G
Required skills
SystemVerilog, UVM, RTL verification, testbench architecture, TCL/Python/Perl scripting, SerDes/PCIe/ARM/DSP/Ethernet familiarity
Preferred skills
Test plan ownership, embedded software (C/Assembly), ARM architecture intuition, AMBA protocol expertise, Linux/GIT/LSF toolchain, leadership, object-oriented design
Technologies
SystemVerilog, UVM, TCL, Python, Perl, SerDes, PCIe, ARM, DSP, Ethernet, AMBA, Linux, GIT, LSF
Responsibilities
Build transaction-level models (TLM), own block and top-level verification sign-off, design UVM testbenches, perform HW emulation and acceleration, bridge hardware/software verification, mentor team members
Seniority
Senior, hands-on IC with team leadership responsibilities
