DFT Architect
Core
Ensure testability and manufacturing quality of next-generation EPYC Server SoCs through DFT implementation, ATPG, and LBIST.
Role type
Senior IC DFT Architect
Builds
Next-gen EPYC Server SoCs for AMD
Domain
Semiconductor / Server CPU
Required skills
DFT architecture, scan design, ATPG, LBIST, Siemens Tessent, fault simulation, coverage analysis, Static Timing Analysis (STA), Perl/Python/Tcl/Shell scripting, ASIC/SoC flows
Preferred skills
Large-scale CPU/GPU/AI/Server SoC experience, MBIST, JTAG, Boundary Scan, IEEE 1500, IJTAG, silicon bring-up, failure analysis, Emulation, Verification, Physical Design flows
Technologies
Siemens Tessent (Mentor TK), Perl, Python, Tcl, Shell
Responsibilities
Collaborate with Architecture teams to define DFT requirements; Partner with Physical Design teams for DFT structure implementation; Develop and execute ATPG strategies; Generate and validate manufacturing test patterns; Perform debug and root-cause analysis of DFT/ATPG/LBIST issues; Support silicon bring-up and yield improvement; Develop automation tools and scripts.
Seniority
Senior, hands-on IC
