Sr ASIC Design Verification Engineer, Low Power AI
Core
Design and verify ultra-low power AI subsystems and audio AI products for next-generation ASICs, focusing on minimizing power consumption and solving power domain crossing challenges.
Role type
Senior IC ASIC design verification engineer (low power AI)
Builds
Ultra-low power SoC HW blocks and audio AI chips
Domain
Semiconductor / VLSI / Low Power AI
Deliverable
production ML models
Required skills
SystemVerilog/UVM, Verilog/VHDL, C/C++, ASIC/VLSI concepts, test bench creation, assertion development, functional coverage modeling, debug leadership, test plan development
Preferred skills
Audio protocols (MP3, MIDI), Bus/interconnect (AHB, AXI), CPU architectures (ARM v8/v7), ISO26262, event-driven simulators, scripting (Perl, Python, tcsh, GNU Make)
Technologies
UVM, SystemC, Verilog, VHDL, C, C++, ARM, AHB, AXI, ISO26262
Responsibilities
Contribute to core verification during pre/post silicon phases, drive test plan development and execution, create/maintain test benches and coverage models, implement automation flows, lead complex debug activities, provide technical supervision, define verification methodology with design teams
Seniority
Senior, hands-on IC with mentorship
