Formal Verification Framework for Hardware IPs Validation
Core
Develop formal verification properties and execute proofs to validate hardware models and subsystems for Apple products.
Role type
Design Verification Engineer (Formal Verification Intern)
Builds
Hardware IPs and complete subsystems for Apple products
Domain
Semiconductor / Hardware Design
Required skills
Formal verification methodologies, SVA, Verilog, VHDL, Mathematical reasoning, Scripting (Perl/Python), Hardware modeling
Responsibilities
Define comprehensive property sets for functional coverage of hardware models, Formalize verification properties using SVA, Execute formal proofs and analyze convergence behavior, Document methodology and best practices for the verification flow, Extend the verification framework to integrate properties at higher levels for system verification
