ASIC Developer
Core
Architect, verify, and scale custom IPs, ASICs, SoCs, and FPGA-based platforms for next-generation communications infrastructure and Layer 1 accelerators using AI-driven verification methodologies.
Role type
Senior Design Verification Engineer (ASIC/SoC/FPGA)
Builds
Custom silicon verification environments, testbenches, and CI/CD pipelines for Layer 1 accelerators, baseband DSPs, and AI/ML inference blocks.
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, assertion-based verification, Python, Tcl, shell scripting, Git, Jenkins, LLM integration, formal verification, C/C++
Preferred skills
JasperGold, UPF/CPF, clock-domain crossing, hardware-software co-verification, Agile methodologies
Technologies
SystemVerilog, UVM, Python, Tcl, Jenkins, Git, JasperGold, LLMs
Responsibilities
Define verification strategies for complex ASICs and SoCs; Architect reusable UVM environments with LLM-assisted test generation; Deploy AI agentic workflows for autonomous triage and test sequence drafting; Drive coverage closure using ML-guided constrained-random and formal verification; Automate and optimize CI/CD pipelines; Verify RTL and gate-level designs across simulation, emulation, FPGA, and post-silicon environments; Mentor junior engineers on verification techniques and AI tools.
Seniority
Senior, hands-on IC
