Senior Engineer ASIC DV
Core
Developing advanced verification components for complex IP designs using UVM methodologies and constrained random verification.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Simulation environments and verification plans for memory and storage IP
Domain
Semiconductor / ASIC Design Verification
Required skills
UVM methodologies, SystemVerilog, constrained random verification, functional coverage closure, Python, IP level verification, block/sub-system test planning, debugging
Preferred skills
AI tools and AI-enabled workflows
Technologies
UVM, SystemVerilog, Python
Responsibilities
Develop UVM-based SystemVerilog test-benches; Define block and sub-system level verification plans; Execute verification plans and interface with design teams; Debug complex problems; Utilize AI tools to improve engineering productivity
Seniority
Senior, hands-on IC
