Foundation IP Design Verification Intern (Summer 2027)
Core
Support design verification for standard-cell libraries, memories, block-level IP, and chip-level integration using circuit simulation, formal verification, and AI-assisted methods.
Role type
IC design verification intern
Builds
Foundation IP libraries and block-level IP for semiconductor manufacturing
Domain
Semiconductor / VLSI Design
Deliverable
production ML models
Required skills
SPICE simulation, Verilog, formal verification, Python scripting, CAD tools, post-silicon analysis, silicon debug, AI-assisted engineering methods
Preferred skills
VLSI design coursework, digital logic, electronic design automation, Perl/Tcl/Shell scripting, project management, leadership experience
Technologies
SPICE, Verilog, Python, Perl, Tcl, Shell, CAD tools
Responsibilities
Perform circuit and logic design verification using SPICE and Verilog simulation; Support verification of Foundation IP including standard-cell libraries and memories; Use AI-assisted methods for performance prediction; Contribute to formal verification activities; Assist with post-silicon analysis and silicon debug; Develop scripts to automate VLSI design and verification tasks; Document methods and communicate findings to the engineering team
