NOC Design Verification Sr Lead Engineer
Core
Lead Design Verification Engineer for next-generation Infrastructure IPs (DDRSS, Memory Controllers) in System-on-chip (SoC) for smartphones, tablets, and other consumer electronics.
Role type
Senior IC Design Verification Architect/Lead Engineer
Builds
Infrastructure IPs and SoCs for mobile and consumer devices
Domain
Semiconductor / Hardware Engineering / SoC Design
Required skills
UVM-based verification, System Verilog, ARM bus protocols, SoC system architecture, Debugging (regression signatures, post-silicon), Functional coverage closure, Test bench ownership (Checkers, Trackers, Scoreboards, Assertions), Scripting (Python/Perl)
Preferred skills
Low-power design verification (clock gating, power collapse), Automotive Safety Integrity Levels (ASIL) verification, Post-silicon bring-up, HW-SW debug, Silicon debug tool chains, C/C++/SystemC for performance modeling
Technologies
UVM, System Verilog, Certitude, VC Formal, VPlan, Python, Perl, C/C++, SystemC, ARM
Responsibilities
Plan and implement IP/Cluster/Formal verification flows, Develop test plans and cases to cover design features, Coordinate with Design and SOC teams, Debug regression signatures and identify bug fixes, Develop/deploy validation scripts and tools, Perform latency and bandwidth analysis, Ensure quality sign-off and documentation
Seniority
Senior, hands-on IC
