Silicon Design Engineer
Core
Develop and execute formal verification strategies for complex USB controller IP and related subsystems to prove design correctness and detect subtle bugs.
Role type
Senior IC formal verification engineer (USB)
Builds
USB controller IP and related subsystems
Domain
Semiconductor / Digital Design
Required skills
formal verification fundamentals, RTL design knowledge, formal methods application, counterexample debugging, root-cause analysis, digital design understanding, finite-state machines, clock/reset behavior, bus protocols, SystemVerilog, SystemVerilog Assertions, formal verification tools (Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal), scripting (Python, Perl, Tcl, shell), UVM, simulation-based verification
Preferred skills
USB protocol experience (USB 2.0, USB 3.x, USB4, xHCI), verification methodology leadership, mentoring
Technologies
Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, SystemVerilog, Python, Perl, Tcl, shell, UVM
Responsibilities
Develop formal verification plans and strategies, build and maintain formal testbenches and assertions, apply formal methods to protocol control logic and state machines, execute property verification and coverage analysis, debug counterexamples with RTL designers, define formal sign-off criteria, improve verification methodology and automation, review specifications for verification risks, partner with simulation DV teams, provide technical guidance and mentoring
Seniority
Senior, hands-on IC
