NPU Design Verification Sr Engineer
Core
Design verification of complex proprietary DSP/NPU IP cores for Qualcomm's multi-tier SoC roadmap targeting mobile, AI, and automotive spaces.
Role type
Senior IC NPU Design Verification Engineer
Builds
High-performance DSP/NPU cores for mobile, AI, and automotive SoCs
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models
Required skills
System Verilog/UVM, Digital Design, Processor Architecture, Power-aware verification, Formal verification, Assertions, Simulation acceleration, Emulation, C/Assembly testcases, Perl/Python/Shell scripting
Preferred skills
UPF, Hardware-SW co-verification, Processor subsystem verification, Object Oriented Programming
Technologies
SystemVerilog, UVM, OVM, Verilog, SystemC, Synopsys, Mentor, Cadence, Perl, Python, Shell, Makefile, TCI
Responsibilities
Drive design verification of DSP IP with global teams; Implement and improve System Verilog/UVM Testbench Architecture; Develop verification environments and test plans; Perform gate-level simulation, timing, and power-aware verification; Debug IP, Subsystem, and SoC level failures; Develop automation for verification activities.
Seniority
Senior, hands-on IC
