NOC DV Engineer
Core
Lead verification of complex AI, Networking, Datacenter, HPC, and Interconnect IPs/Sub-systems to ensure signoff-quality closure.
Role type
Senior IC Design Verification Engineer (NoC/Interconnect/Protocol)
Builds
Next-generation AI and high-performance silicon designs
Domain
Semiconductor / VLSI / Hardware Verification
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, SVA, functional coverage closure, regression management, NoC verification, protocol verification (PCIe, USB, Ethernet, CXL), AMBA protocols, Python, Shell, Perl, Tcl
Preferred skills
SoC verification, AI/ML Accelerators, Networking, Datacenter, Multi-Die, HPC, SystemC/TLM, emulation/prototyping
Technologies
SystemVerilog, UVM, Python, Shell, Perl, Tcl, PCIe, USB, Ethernet, CXL, AMBA, AXI, AHB, ACE, CHI
Responsibilities
Build reusable verification environments (UVCs/agents, sequences, scoreboards, checkers, assertions), execute IP/Sub-System DV from specification review to closure, debug RTL/protocol/architecture issues, verify NoC and high-speed serial protocols, manage regression automation and infrastructure
Seniority
Senior, hands-on IC
