SR ENGINEER, HIG HBM SOC VERIFICATION
Core
Develop test plans, build verification environments, and debug HBM SOC architectures to ensure high-quality memory and storage solutions.
Role type
Senior IC SoC verification engineer (HBM)
Builds
Complex System-on-Chip (SoC) verification environments and test plans for HBM products
Domain
Semiconductor / Memory and Storage / HBM
Required skills
SoC or IP verification, System Verilog, UVM, Gate-level simulation (GLS), Python, UCIE, memory controller, NOCs, MBIST, ATPG scan controllers, DRAM operation, JEDEC specifications
Preferred skills
null
Technologies
System Verilog, UVM, Python, UCIE, NOCs, MBIST, ATPG
Responsibilities
Develop test plans at SOC Level and analyze Coverage, Build verification environments to verify complex SOCs, Develop Random/Directed test in RTL and GLS environments, Review architectural specifications to ensure high quality, Work with customers to understand verification and validation requirements, Engage with customers to support issues with current HBM architectures, Work with IP suppliers to ensure proper verification and validation collaterals are provided, Debug and identify root causes and solutions for pre-silicon and post-silicon issues
Seniority
Senior, hands-on IC
