ASIC Design Verification Engineer
Core
Build verification environments and testbenches for production ASICs that power global 5G networks.
Role type
ASIC Design Verification Engineer
Builds
Production silicon for 5G infrastructure
Domain
Semiconductors / 5G Networks
Required skills
SystemVerilog, UVM, RTL verification, TLM modeling, block/top-level verification, waveform debugging, scripting (TCL/Python/Perl), IP familiarity (SerDes/PCIe/ARM/DSP/Ethernet)
Preferred skills
Directed/randomized test case design, OOP in verification, embedded software design, Linux/GIT/LSF environment, AMBA interfaces (APB/AXI/ACE-Lite/CHI), computer architecture knowledge
Technologies
SystemVerilog, UVM, TLM, TCL, Python, Perl, Linux, GIT, LSF, AMBA, SerDes, PCIe, ARM, DSP, Ethernet
Responsibilities
Build transaction-level models for architectural verification; own coverage closure from block to chip; design and build UVM testbenches from scratch; bridge hardware and embedded software verification; debug RTL issues in waveforms; develop full test plans and test cases
Seniority
Mid-Senior, hands-on IC
