Design Verification Technical Manager (High-Speed IO: PCIe & USB)
Core
Architect and execute comprehensive verification strategies for next-generation high-performance SoCs, focusing on IP-level and subsystem-level verification for mission-critical high-speed serial protocols (PCIe and USB).
Role type
Senior Design Verification Engineer (High-Speed IO: PCIe & USB).
Builds
Modular, scalable UVM-based testbenches and AI/LLM-assisted verification workflows.
Domain
Semiconductor / SoC Design / High-Speed Serial Protocols.
Required skills
UVM, SystemVerilog, SystemVerilog Assertions (SVA), constrained-random test generation, functional coverage analysis, PCIe protocol verification, USB protocol verification, PHY interface verification, LLM/AI integration for verification, automation scripting, regression test management.
Preferred skills
Experience with Gen 4/5/6 PCIe, USB 3.2/4/Type-C, LTSSM state machines, power management states (ASPM, U1/U2/U3), equalization, credit flow control, VIP integration (Synopsys, Cadence), AI prompt engineering.
Technologies
UVM, SystemVerilog, SVA, PCIe, USB, Synopsys VIP, Cadence VIP, LLM tools, automation scripts.
