DFT lead
Core
Define and drive DFT architecture, methodology, and execution for next-generation semiconductor devices, specifically low-cost MCU platforms.
Role type
Senior IC DFT Lead Engineer
Builds
Low-cost MCU silicon designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, scan insertion, ATPG, MBIST, fault simulation, DFT sign-off, Verilog/VHDL, Tcl/Perl/Python scripting, low-power DFT methodologies
Preferred skills
Cross-functional design decision influence, silicon bring-up, ATE correlation, debug, DFT automation flow development
Technologies
Cadence Modus, Genus, Xcelium
Responsibilities
Lead DFT architecture definition for complex SoC designs from concept to tape-out, Drive DFT strategy including scan compression, MBIST, JTAG, and hierarchical test, Represent DFT in cross-functional design reviews and technical forums, Own scan insertion, ATPG, and MBIST implementation for low cost MCU, Define fault coverage targets and ensure test quality standards are met, Lead resolution of complex ATPG, scan chain, and GLS violations, Lead silicon bring-up including ATE correlation and debug, Develop and maintain robust DFT automation flows using Tcl, Perl, and Python
Seniority
Senior, hands-on IC
