Sr. Staff Verification Engineer
Core
Define, develop, and optimize verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits.
Role type
Sr. Staff IC verification engineer (digital/mixed-signal)
Builds
Production ICs with MCU-based hardware systems (ARM, RISC-V, PIC, STM32)
Domain
Semiconductor / Integrated Circuit Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, RTL verification, gate-level verification, AMS verification, constrained-random verification, Python scripting, Perl scripting, EDA tools (Synopsys, Cadence, Siemens), hardware protocols (I2C, I3C, SPI, MIPI), technical leadership
Preferred skills
Analog block behavioral modelling, signal processing, system-level modelling, consumer/ITA market circuit development
Technologies
SystemVerilog, UVM, Verilog, VHDL, Python, Perl, Synopsys, Cadence, Siemens, I2C, I3C, SPI, MIPI
Responsibilities
Define and optimize verification plans and test strategies for digital/mixed-signal ICs; Design and implement complex testbenches using SystemVerilog and UVM; Mentor junior verification engineers; Interface with system, digital hardware, embedded firmware, and analog teams; Drive adoption of advanced verification methodologies; Provide technical support to silicon lab and application engineers
Seniority
Sr. Staff, hands-on IC with mentorship
