Staff DFT Engineer
Core
Own and drive the complete DFT strategy for complex SoCs from architecture through production silicon, ensuring test quality, coverage, and silicon readiness.
Role type
Staff DFT Engineer (Technical Lead)
Builds
Production-ready SoCs with robust testability and high yield
Domain
Semiconductor / ASIC Design / Digital Logic
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (SoC testability)
Required skills
DFT architecture definition, ATPG (stuck-at, transition, path delay), Scan insertion/stitching, LBIST, MBIST, Boundary Scan (IEEE 1149.1), Low-power DFT, JTAG/TAP integration, DFT DRC, Python/Tcl/Perl scripting, RTL design fundamentals, ASIC design flow, EDA tool proficiency (Cadence, Siemens)
Preferred skills
High-volume production test experience, ATE bring-up, Safety-critical application standards (ISO 26262), On-chip debug/trace features
Technologies
Cadence, Siemens, Python, Tcl, Perl, IEEE 1149.1
Responsibilities
Define DFT architecture at chip/subsystem level, Execute ATPG and test compression, Lead silicon bring-up and failure analysis, Mentor junior DFT engineers, Collaborate with RTL, PD, and validation teams
Seniority
Staff, hands-on IC with technical leadership