IP Design Verification Engineer
Core
Design and verify high-speed serial IP blocks (SERDES, PCIe, Ethernet) and security IP (AES, SHA, secure-boot) using UVM-based environments.
Role type
Senior IC IP Design Verification Engineer
Builds
High-reliability, high-performance IP cores for System LSI, Mobile SoCs, and Storage Solutions
Domain
Semiconductor / High-speed Serial Interfaces / Hardware Security
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Formal Verification, High-speed serial protocols (PCIe, Ethernet SERDES), Security IP verification, Simulation tools (VCS, Xcelium, Questa), Coverage-driven verification, Debugging & root-cause analysis, Version control & CI/CD, Digital design fundamentals
Preferred skills
Tcl/Python scripting, SVA, DfT methodologies, Low-power design considerations
Technologies
UVM, System Verilog, VCS, Xcelium, Questa, Git, Jenkins, SVA
Responsibilities
Design and maintain UVM-based verification environments for high-speed serial and security IP; Develop comprehensive test plans and coverage models; Create reusable UVM components; Implement constrained-random traffic generators; Integrate formal verification and assertion-based checking; Run and maintain regression suites; Collaborate with design and security teams to refine specifications and drive DfT; Mentor junior verification engineers; Participate in design reviews and compliance verification
Seniority
Senior, hands-on IC
