Staff Design Verification Engineer – Coherent Interconnect
Core
Drive verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs, focusing on CXL protocol behavior, bridge paths, and subsystem integration.
Role type
Staff individual-contributor design verification engineer
Builds
High-performance SoCs with coherent interconnects (CXL, CHI, ACE, AXI)
Domain
Semiconductor / Chip Design / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments, checkers, scoreboards, assertions, stimulus, coverage models)
Required skills
SystemVerilog, UVM, CXL protocol, cache-coherent systems, on-chip interconnects, memory-subsystem behavior, ordering and flow-control semantics, test plan creation, assertion development, coverage modeling, debugging, Python scripting
Preferred skills
Coherent interconnect/cache/memory-subsystem IP verification, protocol-conversion/bridge-heavy subsystems, formal verification, performance-oriented verification, emulation/FPGA-assisted debug, mentoring
Technologies
SystemVerilog, UVM, Python, CXL, CHI, ACE, AXI
Responsibilities
Drive verification of subsystem behavior across interface boundaries and bridge paths; Develop and maintain robust verification environments, checkers, scoreboards, and coverage models; Define directed and constrained-random scenarios to expose corner cases; Partner with architecture, RTL, and software teams to review specifications and close ambiguities; Analyze failures, isolate root causes, and drive fixes; Contribute reusable methodology and automation improvements; Mentor engineers and raise verification quality across the team
Seniority
Staff, hands-on IC with mentorship
