Emulation Engineer
Core
Building infrastructure, flows, and debug methodology for advanced connectivity SoCs to support high-performance GenAI silicon.
Role type
Senior/Staff Emulation Engineer
Builds
Reusable emulation flows, transactors, agents, and AI-driven tooling for SoC validation.
Domain
Semiconductor hardware design, System-on-Chip (SoC), High-speed connectivity (PCIe, Ethernet, HBM4)
Deliverable
production ML models | product features | infrastructure
Required skills
SoC emulation, Verilog/SystemVerilog, Python, C/C++, Rust, waveform debugging, automation, RTL design, firmware bring-up
Preferred skills
UVM, cycle-accurate models, Bazel, AI/LLM tooling for engineering, chiplet/interconnect fabrics
Technologies
Cadence Palladium, Zebu, Veloce, SpeedBridge, VirtualBridge, SystemC, Tcl, Shell, Rust, C++, Verilog, SystemVerilog
Responsibilities
Define and execute emulation strategy and test plans; Bring up and debug large-scale models on commercial emulation platforms; Integrate external components and build custom transactors; Develop HW/SW co-emulation flows; Drive emulation speed-ups and resource utilization; Build automation for regression triage; Develop practical LLM-based tooling for log analysis and debug assistance.
Seniority
Senior/Staff, hands-on IC
