SR ENGINEER, DDEG DESMETH DFT
Core
Develop verification infrastructure and environments for probe and burn DFT test modes, porting patterns into verification flows, and supporting pre-silicon full-chip and block-level design simulation and debugging.
Role type
Senior IC Digital Design Engineering (DFT) Verification Engineer
Builds
Verification infrastructure, testbenches, vectors, and monitors for DRAM and Emerging Memory architectures
Domain
Semiconductor / Memory (DRAM, NAND, NOR) / Digital Design / DFT
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Constrained Random Verification Methodology, test plan execution, regression testing, functional coverage analysis, simulation debugging, automation scripting, test pattern development
Preferred skills
Experience with DRAM and Emerging Memory architectures, knowledge of post-silicon validation, ability to improve debug efficiency across simulation and silicon loops
Technologies
System Verilog, UVM, Constrained Random Verification Methodology, industry standard and in-house verification programs
Responsibilities
Develop verification infrastructure and environments for DFT test modes; Port probe and burn DFT patterns into verification flows; Provide verification support for pre-silicon full-chip and block-level designs; Develop System Verilog testbench infrastructure; Execute test plans and manage regressions and functional coverage; Assist product engineering with post-silicon validation support; Analyze verification flow gaps and propose solutions; Develop and maintain verification testbenches, vectors, and monitors; Automate simulation data collection; Collaborate on new verification methodologies and strategies
