Principal Quantum Design Verification Engineer
Core
Defining pre- and post-silicon simulation and validation plans for SoC and IP blocks, owning verification environments, and coordinating teams/vendors to deliver high-quality designs.
Role type
Principal Quantum Design Verification Engineer
Builds
Production-ready SoC and IP blocks (CPUs, GPUs, AI accelerators, networking SoCs)
Domain
Semiconductor hardware design verification (Digital, Analog Mixed-Signal, Quantum)
Deliverable
production ML models | product features
Required skills
UVM, OVM, SystemVerilog, C++, C, Python/Ruby/Perl, MATLAB, AMS modeling and simulation, bug tracking, test plan creation, simulation environment setup, DFT collaboration, silicon characterization
Preferred skills
AI tool integration for automation and performance modeling, experience with complex chip verification
Technologies
UVM, OVM, SystemVerilog, Python, Ruby, Perl, C, C++, MATLAB
Responsibilities
Define pre-silicon simulation and post-silicon validation plans for SoC and IP blocks; Own verification environments and tests for IP and SoC designs; Coordinate contingent staff and external vendors to meet specification and schedule; Manage databases, flows, and bug-tracking systems for SoC and IP repositories; Create test plans for pre-silicon simulation across digital and analog components; Align verification methodologies and drive continuous improvement in Design Verification processes
Seniority
Principal, hands-on IC with strategy & mentorship
