DFT Engineer
Core
Developing testability and quality solutions for next-generation semiconductor devices, specifically low-cost MCUs, to ensure silicon-proven test solutions.
Role type
DFT Engineer
Builds
Test solutions for low-cost MCUs and SoC designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (test solutions)
Required skills
DFT architecture design, scan insertion strategies, ATPG test pattern implementation, Memory BIST design, DFT rule compliance, ATPG/scan/GLS debugging, Tcl/Perl/Python scripting, scan compression techniques, IEEE 1149.1/1500 standards knowledge, low-power DFT methodologies
Preferred skills
Experience with Modus EDT/IJTAG, familiarity with automotive grade fault coverage targets
Technologies
EDA tools, Tcl, Perl, Python, Modus EDT, IJTAG
Responsibilities
Develop and execute DFT architecture and scan insertion strategies; Implement and validate ATPG test patterns; Design and deploy Memory BIST solutions; Ensure DFT rule compliance; Debug and resolve ATPG, scan, and GLS violations; Perform DFT sign-off checks; Develop and maintain automation scripts; Improve DFT methodologies
Seniority
Individual Contributor
