Mixed-Signal Verification Engineer – Analog IP
Core
Develop and execute mixed-signal verification solutions for analog IP blocks integrated into digital-on-top SoC environments on the Treo platform.
Role type
Mid-level individual contributor mixed-signal verification engineer
Builds
Scalable digital-on-top testbenches and verification environments for power and clock IP
Domain
Semiconductor IC design, mixed-signal verification, automotive and industrial silicon
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM-based verification, behavioral modeling (Verilog-A/AMS or SystemVerilog real-number), analog IP verification, coverage-driven verification, assertion-based methodologies, regression analysis, root cause debugging
Preferred skills
Power management or clocking architecture knowledge (BGs, PLLs, LDOs, DC/DCs), automotive or industrial silicon reliability experience, automation scripting, AI-assisted verification workflows
Technologies
SystemVerilog, UVM, Verilog-A, AMS, 65nm BCD technology, 300mm fab processes
Responsibilities
Own mixed-signal verification for assigned analog IP blocks; Develop scalable digital-on-top testbenches incorporating behavioral models of analog IP; Translate analog specifications into executable verification plans, assertions, coverage, and checkers; Execute regressions, analyze results, and drive debug to root cause; Verify configuration, calibration, monitoring, and fault-handling interfaces; Coordinate with analog designers, digital verification, and system teams; Create and refine behavioral models for large-scale SoC simulation; Define modeling assumptions and validation strategies; Apply coverage-driven verification practices; Operate with moderate independence while mentoring junior engineers; Provide technical input during IP definition and integration reviews
Seniority
Mid-level, hands-on IC
