Staff Engineer – SoC Design Verification
Core
Provide technical leadership in developing verification strategies for complex analog and mixed-signal SoC designs.
Role type
Staff Design Verification Engineer (SoC/Mixed-Signal)
Builds
Complex analog and mixed-signal SoC designs
Domain
Semiconductor / Mixed-Signal SoC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Mixed-Signal Verification, Advanced Debugging, EDA Tools (Cadence/Synopsys), Python/Perl/TCL/Shell Scripting, Verification Strategy, Coverage Closure
Preferred skills
MS/PhD in EE/CE, 7-10+ years in digital design verification
Technologies
SystemVerilog, UVM, Cadence, Synopsys, Python, Perl, TCL, Shell
Responsibilities
Architect and lead verification strategy for complex digital and mixed-signal designs; Design and implement sophisticated UVM-based verification environments; Guide and develop junior engineers; Coordinate work across organizational lines with design teams; Lead complex debugging efforts across RTL and gate-level simulations; Drive functional and code coverage closure; Lead post-silicon validation activities; Serve as principal customer contact on projects
Seniority
Staff, technical leadership & mentorship
