Sr. Design Verification Engineer - Digital
Core
Developing and implementing verification plans, UVM testbench environments, and regression infrastructure for digital IP blocks, subsystems, and full integrated circuits within mixed-signal sensing products.
Role type
Senior IC design verification engineer (digital/mixed-signal)
Builds
Production-ready digital logic and mixed-signal interfaces for low-power consumer sensing systems (touch, proximity, ADCs)
Domain
Semiconductor / Mixed-signal IC design / Consumer electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Verilog, Python scripting, EDA verification tools (Synopsys VCS, Cadence Xcelium, Siemens Questa), hardware protocols (I2C, I3C, SPI, MIPI), coverage closure, constrained-random verification
Preferred skills
Analog behavioral models (SV-RNM, Verilog-AMS), formal verification (JasperGold, Synopsys VC Formal), Clock Domain Crossing (CDC) sign-off, Low-power verification (UPF/CPF), Lint and structural sign-off, capacitive sensing/touch/proximity IC experience
Technologies
SystemVerilog, UVM, Python, Synopsys VCS, Cadence Xcelium, Siemens Questa, SpyGlass, JasperGold, I2C, I3C, SPI, MIPI, ARM, RISC-V, PIC, STM32
Responsibilities
Define and optimize comprehensive verification plans and test strategies for digital IP and full-chip verification; Design and implement UVM testbench environments and debug complex simulation failures; Supervise and mentor junior verification engineers; Support silicon lab evaluation, performance characterization, and debug; Drive adoption of advanced verification methodologies and tool evaluation; Interface with system, digital hardware, embedded firmware, and analog teams
Seniority
Senior, hands-on IC with technical leadership
