Staff Physical Verification Engineer
Core
Own full-chip physical verification signoff for advanced SoC/ASIC designs, ensuring tape-out readiness from block-level checks to final GDS delivery.
Role type
Staff Physical Verification Engineer (IC Design)
Builds
Production-ready silicon for complex SoCs/ASICs
Domain
Semiconductor / Physical Design / Advanced Process Nodes (5nm+)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: physical/clinical work -> infrastructure/physical work context, but strictly following schema: 'production ML models' is wrong. Let's re-evaluate 'Deliverable'. The role produces clean GDS and signoff. This maps best to 'product features' (the chip) or 'infrastructure' (the flow). However, the schema options are specific. 'product features' fits the chip design best. Let's use 'product features' as the chip is the product feature being verified. Wait, the schema says 'one of: ...'. Let's look at the options again: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. A chip verification engineer ensures the 'product features' (the chip functionality) are physically realizable. Alternatively, they build the 'infrastructure' (PV flows). Given 'own full-chip signoff', 'product features' is the most accurate representation of the *object* being delivered/verified, though 'infrastructure' describes the *method*. Let's choose 'product features' as the primary output of the verification effort is the validated chip design.
Required skills
Full-chip DRC/LVS/PERC signoff ownership, Advanced node (5nm/sub-7nm) FinFET process expertise, Calibre/ICV tool mastery, Python/Perl/Tcl/Unix scripting, Floorplanning and power grid planning, Cross-functional technical leadership, Foundry/EDA vendor interface management
Preferred skills
Digital-on-top/mixed-signal SoC experience, DFM/DFY check familiarity, Hierarchical flow and IP integration experience
Technologies
Siemens Calibre, Synopsys IC Validator, Cadence Virtuoso-PV, Python, Perl, Tcl, Unix shell
Responsibilities
Own full-chip and block-level physical verification signoff (DRC, LVS, ERC, PERC, ESD), Drive tape-out readiness and manage PV schedules, Develop and optimize PV flows and scripts, Define and enhance PERC/reliability rule checks, Own floorplanning and power grid planning, Debug complex DRC/LVS/PERC violations, Partner with CAD teams for technology node validation, Mentor engineers on PV best practices, Act as primary interface to foundry and EDA vendors
Seniority
Staff, hands-on IC with strategic ownership and mentorship