MTS-RTL Verification Engineer
Core
Architect and develop scalable verification environments for high-speed digital designs in advanced process nodes.
Role type
Senior RTL Verification Engineer (High-Speed Digital)
Builds
Verification environments, testbenches, and closure metrics for memory and storage products.
Domain
Semiconductor / High-Speed Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (verification environments)
Required skills
SystemVerilog, UVM, Constrained-Random Testing, Formal Verification, Clock/Reset/FSM/CDC fundamentals, Debug, Python/Perl/Tcl scripting
Preferred skills
Power-aware verification, High-speed memory subsystems, Global cross-site team collaboration
Technologies
SystemVerilog, UVM, Formal Verification, Python, Perl, Tcl
Responsibilities
Own verification strategy and planning, Architect reusable verification environments, Drive functional and code coverage closure, Lead debug and issue resolution, Provide verification status and risk assessments, Improve verification methodologies and automation, Mentor engineers
Seniority
Senior, hands-on IC
