Staff Design Verification Engineer
Core
Develop SystemVerilog/UVM testbenches for unit-level verification of Memory Controller functional units, ensuring PPA goals are met.
Role type
Staff Design Verification Engineer (Memory Controller)
Builds
Validated RTL models for Arm AMBA systems and Memory Controllers
Domain
Semiconductor / SoC Design / Memory Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Python, Perl, SystemVerilog Assertions, RTL debugging, Functional coverage, Microarchitecture knowledge
Preferred skills
DRAM specifications (LPDDR4/5, DDR4/5, HBM), Bus protocols (AMBA5 CHI, AMBA4 ACE, AXI), SoC systems knowledge
Technologies
SystemVerilog, UVM, Python, Perl, AMBA
Responsibilities
Develop SystemVerilog/UVM testbenches for unit level focusing on Memory Controller verification; Build and maintain detailed verification plans; Generate and run test cases on logic simulation models; Debug functional errors in the RTL model using simulation and debug tools; Define and implement functional coverage
Seniority
Staff, hands-on IC
